In the fabrication of a trench capacitor DRAM, the capacitor at the bottom of the trench is connected to the lower electrode of the vertical transistor through a diffused area called a buried strap that is typically formed in the single crystal silicon substrate by depositing a doped layer of polycrystalline silicon (poly) and in a heat treatment diffusing the dopant out into the single crystal substrate.
In contemporary practice, the buried strap is formed by opening an aperture in the insulating sidewall of the trench and diffusing dopant into the bulk single-crystal silicon to make a path out of the trench, into the silicon and vertically upward to contact the lower electrode of the vertical transistor.
One problem with this approach is that it requires a large out-diffusion in order to ensure overlap between the strap and the channel of the vertical device. The diffusion from the buried strap must extend vertically sufficiently that the P-N junction between the buried strap and the channel is within the range of control of the transistor gate—i.e. that there is not a length of silicon between the lower electrode of the transistor and the channel that would not be inverted. The overlap must be sufficient to work throughout the range of dimensions that result from processing variations.
The depth and width of the buried strap are limited to the collar oxide thickness and the aspect ratio requirements of the process. If the designer tries to make the buried strap layer too thick, it will block the upper portion of the aperture, leaving a void.